本教材凝聚编者十多年教学与科研经验，采用“基础原理—实用模块—综合设计”三级递进架构，内容包括 EDA 技术与可编程逻辑设计、EDA 技术硬件原理、VHDL 基本语法、Quartus 软件的使用、VHDL数字系统设计基本技能以及综合设计应用实例，全面覆盖现代数字系统开发的全过程。 本教材突出代码驱动和实战训练特色，提供丰富的可运行实例和调试专题，所有案例均源自工程实践，既适合作为高等院校电子信息、微电子、集成电路等相关专业的课程教材，也可供 FPGA/CPLD 开发爱好者参考使用。通过本教材的学习，读者将能够独立完成基础数字系统的设计与开发。

彭元杰，电子信息实验室主任，湖南文理学院，主要研究方向为数字集成电路设计等。近年来，在国内外学术期刊发表学术论文10余篇；主持和参与省级科研课题、教改课题共5项。担任实验室主任15年，指导学生参加各类竞赛，获国家 级一等奖1项，二等奖2项，三等奖1项，省级一等奖3项，二、三等奖若干。参与主编教材1部。 担任“EDA技术”“数字集成电路设计”“PCB工艺与设计”课程本科教学10余年，长期指导学生课程设计。

第1 章 EDA 技术与可编程逻辑设计 ············································································ 1 1.1 EDA 技术的含义与应用 ·························································································· 3 1.2 EDA 技术的发展 ··································································································· 4 1.3 传统设计方法：Bottom-up 及其局限性 ······································································· 5 1.4 现代设计范式：Top-down 设计方法 ··········································································· 6 1.4.1 核心流程 ···································································································· 6 1.4.2 核心优势 ···································································································· 6 1.5 IP 核复用与SoC 设计 ···························································································· 7 1.5.1 IP 核分类与技术特点 ····················································································· 7 1.5.2 SoC 设计 ···································································································· 7 1.6 现代数字系统设计流程 ··························································································· 8 1.7 常用EDA 工具软件 ······························································································· 9 1.8 可编程逻辑设计的本质 ·························································································· 11 本章小结 ·················································································································· 12 习题 ························································································································ 13 第2 章 EDA 技术硬件原理 ························································································· 14 2.1 可编程逻辑器件概述 ····························································································· 16 2.1.1 PLD 分类 ··································································································· 16 2.1.2 PLD 技术发展 ····························································································· 17 2.2 PLD 电路的表示方法 ···························································································· 18 2.3 SPLD 结构与原理 ································································································ 19 2.4 CPLD 结构与原理 ································································································ 23 2.5 FPGA 结构与原理 ································································································ 25 2.5.1 查找表结构 ································································································ 25 2.5.2 Cyclone Ⅳ器件结构 ····················································································· 27 2.6 硬件测试技术 ······································································································ 29 2.6.1 内部逻辑测试 ····························································································· 29 2.6.2 JTAG 边界扫描测试 ····················································································· 30 2.7 FPGA/CPLD 的编程与配置 ····················································································· 31 2.7.1 在系统可编程 ····························································································· 31 2.7.2 FPGA 器件的配置 ························································································ 31 2.7.3 Cyclone Ⅳ器件的编程 ·················································································· 32 2.8 FPGA/CPLD 器件概述 ··························································································· 33 2.9 开发板选购指南 ··································································································· 35 本章小结 ·················································································································· 36 习题 ························································································································ 36 第3 章 VHDL 基本语法 ······························································································ 38 3.1 VHDL 的特点 ····································································································· 40 3.2 VHDL 程序基本结构 ···························································································· 40 3.3 VHDL 文字规则 ·································································································· 42 3.3.1 数字与字符 ································································································ 42 3.3.2 字符串与位矢量 ·························································································· 43 3.3.3 关键词 ······································································································ 44 3.3.4 标识符及其表述规则 ···················································································· 44 3.3.5 VHDL 的空白符 ·························································································· 45 3.3.6 文件取名和存盘 ·························································································· 45 3.3.7 规范的程序书写格式 ···················································································· 46 3.4 VHDL 程序主要构件 ···························································································· 46 3.4.1 库声明 ······································································································ 46 3.4.2 程序包的使用 ····························································································· 47 3.4.3 实体 ········································································································· 48 3.4.4 结构体 ······································································································ 50 3.4.5 配置-可选 ·································································································· 51 3.5 VHDL 数据对象 ·································································································· 52 3.5.1 常量 ········································································································· 52 3.5.2 变量 ········································································································· 53 3.5.3 信号 ········································································································· 54 3.5.4 信号与变量的比较 ······················································································· 55 3.6 VHDL 数据类型 ·································································································· 56 3.6.1 标准数据类型 ····························································································· 56 3.6.2 用户自定义数据类型 ···················································································· 57 3.6.3 数据类型转换 ····························································································· 58 3.7 VHDL 运算符 ····································································································· 59 3.7.1 算术运算符 ································································································ 59 3.7.2 逻辑运算符 ································································································ 59 3.7.3 关系运算符 ································································································ 60 3.7.4 其他运算符 ································································································ 60 3.7.5 运算符优先级 ····························································································· 61 3.8 VHDL 基本语句 ·································································································· 61 3.8.1 并行语句 ··································································································· 61 3.8.2 VHDL 顺序语句 ·························································································· 70 3.8.3 VHDL 属性描述语句 ···················································································· 75 3.9 VHDL 其他构件 ·································································································· 80 3.9.1 块 ············································································································ 80 3.9.2 函数 ········································································································· 82 3.9.3 过程 ········································································································· 83 3.9.4 程序包 ······································································································ 84 3.10 结构体的描述方法 ······························································································ 86 3.11 测试基准 ·········································································································· 88 本章小结 ·················································································································· 89 习题 ························································································································ 90 第4 章 Quartus 软件的使用 ······················································································· 93 4.1 Quartus 软件版本与功能 ························································································ 95 4.1.1 Quartus 软件各版本功能变迁 ·········································································· 95 4.1.2 Quartus 软件版本的选择 ················································································ 96 4.1.3 Quartus 软件功能特点 ··················································································· 96 4.2 Quartus 软件的安装 ······························································································ 97 4.3 Quartus 的文件 ···································································································· 98 4.3.1 文件扩展名 ································································································ 98 4.3.2 文件名相应规则 ·························································································· 99 4.4 Quartus Prime 设计的流程 ···················································································· 100 4.5 Quartus Projects ·································································································· 102 4.6 设计输入 ·········································································································· 103 4.6.1 文本输入 ································································································· 103 4.6.2 原理图输入 ······························································································ 108 4.6.3 顶层实体 ·································································································· 111 4.7 全编译 ············································································································· 112 4.7.1 编译过程原理 ··························································································· 112 4.7.2 可综合性概述 ··························································································· 112 4.8 仿真 ················································································································ 114 4.8.1 仿真概述 ································································································· 114 4.8.2 功能仿真与时序仿真 ·················································································· 115 4.9 引脚配置与基于IP 核的设计 ················································································ 124 4.9.1 基本引脚配置方法 ····················································································· 124 4.9.2 Quartus Prime 基于IP 核的设计 ····································································· 130 4.10 keep 属性应用与Signal Probe Pins 的使用 ······························································· 139 4.10.1 Signal Probe Pins 的作用与优势 ···································································· 139 4.10.2 keep 属性应用 ························································································· 139 4.10.3 Signal Probe Pins 详细使用步骤 ···································································· 140 4.11 ROM IP 核与Signal Tap Logic Analyzer 的使用 ························································· 142 4.12 Signal Tap Logic Analyzer 与Signal Probe Pins 的区别 ················································ 149 4.13 LPM 嵌入式锁相环（PLL）应用 ·········································································· 149 4.13.1 建立嵌入式PLL 元件 ················································································ 149 4.13.2 FPGA 中PLL 应用要注意的问题 ·································································· 153 4.14 Quartus Prime 的优化设置 ·················································································· 153 4.14.1 编译设置 ································································································ 153 4.14.2 网表查看器（Netlist Viewer） ····································································· 154 4.14.3 器件资源利用报告 ···················································································· 154 4.14.4 设计可靠性检查 ······················································································· 155 4.14.5 利用Optimization Advisors（优化指导）工具对设计进行优化 ····························· 155 本章小结 ················································································································ 156 习题 ······················································································································ 157 第5 章 VHDL 数字系统设计基本技能 ······································································· 159 5.1 组合逻辑电路的设计 ··························································································· 161 5.1.1 组合逻辑电路的特点与组成 ········································································· 161 5.1.2 组合逻辑电路的设计原则 ············································································ 162 5.1.3 常见组合逻辑电路的VHDL 描述 ·································································· 166 5.2 时序逻辑电路的设计 ··························································································· 192 5.2.1 时序逻辑电路的分类与设计原则 ··································································· 192 5.2.2 常见时序逻辑电路的VHDL 描述 ·································································· 197 5.3 VHDL 中相似功能语法分析 ················································································· 218 5.4 寄存器的引入与重要注意事项 ··············································································· 221 5.5 时序逻辑电路的描述方法 ····················································································· 224 5.5.1 ASM 图描述 ····························································································· 224 5.5.2 VHDL 描述 ······························································································ 226 本章小结 ················································································································ 241 习题 ······················································································································ 242 第6 章 综合设计应用实例 ························································································ 246 6.1 七段数码管动态扫描显示 ····················································································· 248 6.1.1 基本原理 ································································································· 248 6.1.2 项目设计 ································································································· 249 6.2 矩阵键盘识别 ···································································································· 252 6.2.1 基本原理 ································································································· 252 6.2.2 项目设计 ································································································· 252 6.3 LCD1602 液晶屏字符驱动 ···················································································· 258 6.3.1 基本原理 ································································································· 258 6.3.2 项目设计 ································································································· 262 6.4 VGA 显示控制 ·································································································· 263 6.4.1 基本原理 ································································································· 263 6.4.2 项目设计 ································································································· 264 6.5 电 机 控 制 ····································································································· 269 6.5.1 基本原理 ································································································· 269 6.5.2 项目设计 ································································································· 270 6.6 红外遥控信号接收处理 ························································································ 274 6.6.1 基本原理 ································································································· 274 6.6.2 项目设计 ································································································· 274 6.7 数字密码锁设计 ································································································· 276 6.7.1 基本原理与功能设计 ·················································································· 276 vii 目 录 6.7.2 项目设计 ································································································· 277 6.8 音乐播放器的设计 ······························································································ 281 6.8.1 乐谱到声音的转换原理 ··············································································· 281 6.8.2 音乐播放器的功能需求 ··············································································· 281 6.8.3 整体方案设计 ··························································································· 282 6.8.4 系统设计实现 ··························································································· 282 6.9 简易DDS 正弦信号发生器的设计 ·········································································· 290 6.9.1 DDS 原理 ································································································· 291 6.9.2 设计方案与实现 ························································································ 292 6.9.3 功能扩展 ································································································· 296 6.9.4 使用Signal Tap Logic Analyzer 观测输出波形 ···················································· 298 6.9.5 硬件调试 ································································································· 299 本章小结 ················································································································ 299 综合训练课题 ·········································································································· 300 参考文献 ···················································································································· 302